1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly relates to a semiconductor device utilizing a planarizing process by CMP (Chemical Mechanical Polishing) and a manufacturing method thereof.
2. Description of Related Art
CMP is often used for planarizing a surface of respective layers in manufacturing of semiconductor devices. In the planarizing process by CMP, dummy patterns for CMP (hereinafter called, “CMP dummy patterns” or merely “dummy pattern (s)”) are arranged so as to avoid occurrence of dishing and erosion (see Japanese Patent Application Laid-open No. 2006-39587). Generally, the size, number, and arrangement of the CMP dummy patterns are determined to be optimized in the respective layers subject to CMP.
Recently, however, as for more miniaturized semiconductor devices, the following problems have been found when optical inspections are performed to detect defects such as particles and short circuits of patterns.
That is, smaller defects and particles must be detected because of miniaturizing of devices and thus the detection sensitivity needs to be increased. When the detection sensitivity is increased, however, a difference between a dummy pattern in an upper layer and a dummy pattern in a lower layer may appear as moire (interference fringe), because the dummy patterns are arranged to be optimized in the respective layers as described above. Thus, in defect inspections, such moire may be detected as a defect and defects caused by moire may be mixed with particles and defects that should be detected originally, and all of them may be detected as defects, resulting in an increased number of defects. On the other hand, when the detection sensitivity is decreased to prevent generation of moire, minute particles and defects cannot be detected, causing a decrease in yield.